ff-ad9833 project: musical notes and melody system implemented

ad9833-based audio module

I added two modules to my ff-ad9833: one called notes which handles playing music and rest notes, and another called score which provides a convenient way to lay out a melody of notes in memory and to play them at an arbitrary tempo. My first simple demo is the “Are You Sleeping” tune:

I defined some Forth words such that it is fairly natural to lay out the notes in a memory block. This is what “Are You Sleeping” looks like in Forth code:

flash

create rusleeping
d_quarter nc o5 == d_quarter nd o5 == d_quarter ne o5 == d_quarter nc o5 ==
d_quarter nc o5 == d_quarter nd o5 == d_quarter ne o5 == d_quarter nc o5 ==
d_quarter ne o5 == d_quarter nf o5 == d_half    ng o5 ==
d_quarter ne o5 == d_quarter nf o5 == d_half    ng o5 ==
d_8th     ng o5 == d_8th     na o6 == d_8th     ng o5 == d_8th     nf o5 ==
d_quarter ne o5 == d_quarter nc o5 ==
d_8th     ng o5 == d_8th     na o6 == d_8th     ng o5 == d_8th     nf o5 ==
d_quarter ne o5 == d_quarter nc o5 ==
d_quarter nc o5 == d_quarter ng o4 == d_half    nc o5 ==
d_quarter nc o5 == d_quarter ng o4 == d_half    nc o5 ==
d_half    nc o5 == d_half    nr nr == d_half    ng o4 == d_half    nr nr ==
d_whole   nc o5 == d_8th     nc o5 == end-score

ram

Each note, including duration, pitch, and octave, is packed automatically into one 16-bit memory cell, so that not a lot of memory is used.

This music system is not really sophisticated enough to use for something like a video game console, since the ad9833 does not have ADSR envelopes or anything like that. But perhaps it would be useful for something like a simple toy, or part of the interface of some appliance.

It has been a lot of fun coding these modules, as well as writing the comment documentation. I developed my own source code documentation standard for the project to keep the code documentation clean and organized.

I learned in the process about the reuse software, which has a nifty reuse lint command which helped me in placing proper licensing and copyright documentation in all my code files. Most free software coders I have come across think very little, if at all, about proper code licensing details. But it is important to make the licensing clear, and clear on all files in the project, so as to make it easier for others to reuse, modify, and share the code with confidence.

While this component of the project is nearly complete, I had thoughts of adding one more demo tune — something longer and more sophisticated. As far as the ff-ad9833 project itself, I had thoughts of adding one more module for generating Audio FSK data communication capabilities. Like, for amateur radio RTTY.

The code for the ff-ad9833 project is available to download from this repository:

https://codeberg.org/infrared/ff-ad9833

In the picture at the top of this post, the audio module is being powered by the Arudino UNO 5V VCC pin. However, it is better instead to power the audio module from a separate 5V power supply (at least 3W). You can then tie the DGND pin on the audio module to a GND pin on the UNO, and also tie the other GND pin on the UNO to the ground or negative lead on the 5V power supply. In my experiments, this resulted in more stable audio module operation, as well as cleaner sound at the higher volume levels.

I think, if I were redesigning my audio module, I might also utilize a diode to prevent current from rushing back from the audio module into the UNO. I’m not quite sure if that is really necessary, but it seems like a good idea.

ff-ad9833 Repo

codeberg repository for ad9833-related FlashForth code

For my on-going exploration of ad9833 audio generation using FlashForth 5, a code repository is now available at codeberg:

https://codeberg.org/infrared/ff-ad9833

So far, I have a demo-pitches word that plays c4, e4, g4, and c5 frequencies, but I can set other frequencies ranging from a4 to g#6, using the words I have so far. There is no system yet for setting duration, so I can’t play notes proper. But it was fun setting up a system for setting the equal temperament pitches.

In microcontroller programming, it is much easier to justify efforts to save memory. I needed to store the precalculated frequency register data values for each pitch. Originally I had a table like so:

$5274 , $4000 ,
$538d , $4000 , 
$54b7 , $4000 ,
$55f2 , $4000 ,
...
$4b5a , $4002 ,

With each line (two 16 bits words) representing one pitch. However, the first two bits in each 16-bit word are actually not frequency data, but register addressing bits, which can easily be added in later. Also, the second 16-bit word in each pair has (in my application) only two bits of actual frequency data, which are the two right most bits. So, I cut the table memory usage in half by packing those two bits into the left-most two bits of the first word in each pair:

\ packaged freq register data for equal temp
\ pitches from A4, A#4, B4 , ... , G#6
\ format numbered from lsb to msb:
\ 0-13: the 14 LSBs of the lsb register load
\ 14-15: the 2 LSBs of the msb register load

create packed-pitches
$1274 , $138d ,
$14b7 , $15f2 ,
$1740 , $18a2 ,
$1a19 , $1ba7 ,
...

Now each line in the table is actually two separate pitches. Then I just need a few words to separate the bits back out into separate words, and recombine them with the frequency register addressing bits:

0  constant na
1  constant na#
2  constant nb
3  constant nc
4  constant nc#
5  constant nd
6  constant nd#
7  constant ne
8  constant nf
9  constant nf#
10 constant ng
11 constant ng#

0 constant o4
1 constant o5
2 constant o6

: pull-pitch ( note octave -- u ) 12 * + cells packed-pitches + @ ;

: pull-14lsb %0011111111111111 and ;

: pull-2msb %1100000000000000 and 14 rshift ;

%0100000000000000 constant FREG0

: tx-pitch ( note octave -- )
    pull-pitch cp>r pull-14lsb FREG0 or 2tx-spi
    r> pull-2msb FREG0 or 2tx-spi ;

In testing, I have some trouble with some pitches getting distorted when I set the volume to higher levels. I suspect the problem is that I am still using the USB power supply and need to feed in my +5V from an external PS. I plan to try that next week, God willing.

AD9833 Signal Driven by Flash Forth

400 Hz signal from an AD9833 module, initialized by 328P MC running FlashForth

Having figured out how to configure the parameters of the SPI bus, and transmit bytes, I wanted then drive my AD9833 module, which is a frequency generator.

Arduino Uno running FlashForth connected to a GY-9833 module, which is a dev module for the AD9833 signal generator chip

I determined from the datasheet that I would need the SCLK signal to be high on idle, and to sample on the leading edge. Also, fsync needs to go low before the data is transmitted.

Timing Diagrams for AD9833 chip

Here are the FSYNC, SCK, and data signals on a scope:

FSYNC signal is yellow, SCK signal is green, and data signal is purple

I actually had to study these signals for a few minutes because at first the initialization code was not working. I released that there was a bug in my code such that the fsync signal was inverted. That was easy to fix.

The above data translates to this example initialization data from the programmer’s guide:

Zooming in, you can see the first byte, 0x21:

First byte’s worth of signals

With sampling on leading edge of SCK (green signal) we have 00100001, i.e., 0x21.

Here is the code so far:

\ ad9833.fs

\ Copyright 2021 Christopher Howard

\ Licensed under the Apache License, Version 2.0 (the "License");
\ you may not use this file except in compliance with the License.
\ You may obtain a copy of the License at

\     http://www.apache.org/licenses/LICENSE-2.0

\ Unless required by applicable law or agreed to in writing, software
\ distributed under the License is distributed on an "AS IS" BASIS,
\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
\ See the License for the specific language governing permissions and
\ limitations under the License.

ad9833
marker ad9833

: init-spi ( -- )
    \ set data direction bits
    DD_OUT DD_MOSI lshift
    DD_OUT DD_SCK  lshift or
    DD_OUT DD_SS   lshift or DDR_SPI mset
    \ Setup control register
    1           SPR0 lshift
    0           SPR1 lshift or \ fck/16
    CPHA_SMPLED CPHA lshift or
    CPOL_HIDLE  CPOL lshift or
    MSTR_MSTR   MSTR lshift or 
    DORD_MSB    DORD lshift or
    SPE_ENAB    SPE  lshift or
    SPIE_DISAB  SPIE lshift or SPCR c!
;

: init-fsync [ DD_OUT #4 lshift ] literal DDRD mset ;

: fsync-low [ 1 #4 lshift ] literal PORTD mclr ;

: fsync-high [ 1 #4 lshift ] literal PORTD mset ;

: demo-400hz
    init-spi
    init-fsync
    fsync-low
    $21 tx-spi $00 tx-spi
    $50 tx-spi $c7 tx-spi 
    $40 tx-spi $00 tx-spi 
    $c0 tx-spi $00 tx-spi 
    $20 tx-spi $00 tx-spi
    fsync-high
;

\ Only for viewing the SPI signals
: test-demo begin demo-400hz 1 ms again ;

First you have to load this ad9833 code:

\ ff-328p.fs

\ Copyright 2021 Christopher Howard

\ Licensed under the Apache License, Version 2.0 (the "License");
\ you may not use this file except in compliance with the License.
\ You may obtain a copy of the License at

\     http://www.apache.org/licenses/LICENSE-2.0

\ Unless required by applicable law or agreed to in writing, software
\ distributed under the License is distributed on an "AS IS" BASIS,
\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
\ See the License for the specific language governing permissions and
\ limitations under the License.

ff-328p
marker ff-328p

\ General I/O port addresses

$25 constant PORTB
$28 constant PORTC
$2b constant PORTD

\ Data Direction Registers

$24 constant DDRB
  1 constant DD_OUT
  0 constant DD_IN
$2a constant DDRD

\ DDR for SPI comms

$24 constant DDR_SPI
$2 constant DD_SS
$3 constant DD_MOSI
$5 constant DD_SCK

\ SPI control register

$4c constant SPCR
$0 constant SPR0 \ SPI Clock Rate Selector bits
$1 constant SPR1 \ (see table 18-5 in 328P datasheet)
$2 constant CPHA \ Clock Phase bit
  1 constant CPHA_SMPTRL \ sample on trailing edge of SCK
  0 constant CPHA_SMPLED \ sample on leading edge of SCK
$3 constant CPOL \ Clock Polarity bit
  1 constant CPOL_HIDLE \ SCK high when idle
  0 constant CPOL_LIDLE \ SCK low when idle
$4 constant MSTR \ Master/Slave Select bit
  1 constant MSTR_MSTR \ master mode
  0 constant MSTR_SLAVE \ slave mode
$5 constant DORD \ Data Order bit
  1 constant DORD_LSB \ LSB transmitter first
  0 constant DORD_MSB \ MSB transmitted first
$6 constant SPE \ SPI Enable bit
  1 constant SPE_ENAB \ SPI enabled
  0 constant SPE_DISAB \ SPI disabled
$7 constant SPIE \ SPI Interrupt Enable bit
  1 constant SPIE_ENAB \ SPI Interrupt Enabled
  0 constant SPIE_DISAB \ SPI Interrupt Disabled

\ SPI status register

$4d constant SPSR 
$0 constant SPI2X \ Double SPI Speed Bit
$6 constant WCOL \ Write COLlision Flag
$7 constant SPIF \ SPI Interrupt Flag

\ SPI Data Register (i/o port)

$4e constant SPDR

: tx-spi ( c -- )
    SPDR c! begin SPSR c@ 1 SPIF lshift and until
;

2d Array Problem in Gforth

Standard Forth includes the ability to define classes of memory objects, along with an instance behavior for that class. It’s a little like OOP, but without inheritance and with only one class method. Basically, it is a way to add a forth word which can be used to initialize memory and map it to a name, and then use that new name as an interface to the memory. The forth words constant and variable are such words, which define in memory a constant or a variable. Then the name of said constant or variable can be called on to return the value of the constant or the address of the variable’s storage memory.

One problem from Forth Application Techniques is to create a 2D array class. Here is a (non-optimized) solution:

: 2< ( n0 n1 n2 n3 -- b ) rot > -rot < and ;

: 4dup ( n0 n1 n2 n3 -- n0 n1 n2 n3 n0 n1 n2 n3 )
    3 pick 3 pick 3 pick 3 pick ;

: 2array ( n0 n1 -- ) create 2dup , , * cells allot
  does> ( n0 n1 -- a )
    dup >r 2@ 4dup 2< 0= if -24 throw then
    swap 2 pick * nip nip + cells r> + 2 cells + ;

The first two words, 2< and 4dup are some helper words.

The first line of 2array is the defining action, which takes two numbers of the stack and stores them in the memory space to serve as dimensions for the array. Further memory is allotted according to the dimensions given. create associates the memory with the instance word.

The code for 2array after does> is the instance behavior, which takes two index numbers off the stack, and returns the correct memory address. The first line of the instance behavior code serves to confirm that the indices are not larger than the array dimensions. The second line then calculates the appropriate memory address and drops it on the stack.

Here is defining a 3×2 array:

3 2 2array data  ok

In Gforth our cell size is 8 bytes, so our memory address increments by 8 as we move through the array:

0 0 data . 140051427947736  ok
1 0 data . 140051427947744  ok
2 0 data . 140051427947752  ok
0 1 data . 140051427947760  ok
1 1 data . 140051427947768  ok
2 1 data . 140051427947776  ok

If we go too large, we throw an error:

0 2 data . 
:19: Invalid numeric argument
0 2 >>>data<<< .
Backtrace:
$7F60439CF420 throw 
$7F60439CF4C8

Of course, we can store things in our array:

0 0 0 data !  ok
1 1 0 data !  ok
2 2 0 data !  ok
3 0 1 data !  ok
4 1 1 data !  ok
5 2 1 data !  ok
0 0 data 3 2 * cells dump 
7F60439CF4D8: 00 00 00 00  00 00 00 00 - 01 00 00 00  00 00 00 00  ................
7F60439CF4E8: 02 00 00 00  00 00 00 00 - 03 00 00 00  00 00 00 00  ................
7F60439CF4F8: 04 00 00 00  00 00 00 00 - 05 00 00 00  00 00 00 00  ................
 ok

FlashForth SPI (328P)

example 0: byte 0xDE sent using SPI (green) and SCK driver signal (yellow). Common SPI configuration.

I wrote some some FlashForth code to be able to initialize the SPI system on the 328P, and transmit bytes – a more thorough version of what I had done earlier with Arduino-FVM. It basically amounted to a list of SPI-related register and bit constants.

\ ff-328p.fs

\ Copyright 2020 Christopher Howard

\ Licensed under the Apache License, Version 2.0 (the "License");
\ you may not use this file except in compliance with the License.
\ You may obtain a copy of the License at

\     http://www.apache.org/licenses/LICENSE-2.0

\ Unless required by applicable law or agreed to in writing, software
\ distributed under the License is distributed on an "AS IS" BASIS,
\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
\ See the License for the specific language governing permissions and
\ limitations under the License.

ff-328p
marker ff-328p

\ General I/O port addresses

$25 constant PORTB
$28 constant PORTC
$2b constant PORTD

\ Data Direction Registers

$24 constant DDRB
  1 constant DD_OUT
  0 constant DD_IN

\ DDR for SPI comms

$24 constant DDR_SPI
$2 constant DD_SS
$3 constant DD_MOSI
$5 constant DD_SCK

\ SPI control register

$4c constant SPCR
$0 constant SPR0 \ SPI Clock Rate Selector bits
$1 constant SPR1 \ (see table 18-5 in 328P datasheet)
$2 constant CPHA \ Clock Phase bit
  1 constant CPHA_SMPTRL \ sample on trailing edge of SCK
  0 constant CPHA_SMPLED \ sample on leading edge of SCK
$3 constant CPOL \ Clock Polarity bit
  1 constant CPOL_HIDLE \ SCK high when idle
  0 constant CPOL_LIDLE \ SCK low when idle
$4 constant MSTR \ Master/Slave Select bit
  1 constant MSTR_MSTR \ master mode
  0 constant MSTR_SLAVE \ slave mode
$5 constant DORD \ Data Order bit
  1 constant DORD_LSB \ LSB transmitter first
  0 constant DORD_MSB \ MSB transmitted first
$6 constant SPE \ SPI Enable bit
  1 constant SPE_ENAB \ SPI enabled
  0 constant SPE_DISAB \ SPI disabled
$7 constant SPIE \ SPI Interrupt Enable bit
  1 constant SPIE_ENAB \ SPI Interrupt Enabled
  0 constant SPIE_DISAB \ SPI Interrupt Disabled

\ SPI status register

$4d constant SPSR 
$0 constant SPI2X \ Double SPI Speed Bit
$6 constant WCOL \ Write COLlision Flag
$7 constant SPIF \ SPI Interrupt Flag

\ SPI Data Register (i/o port)

$4e constant SPDR

: tx-spi ( c -- )
    SPDR c! begin SPSR c@ 1 SPIF lshift and until
;

Here are some examples:

\ a common configuration
: init-spi-ex0 ( -- )
    \ set data direction bits
    DD_OUT DD_MOSI lshift
    DD_OUT DD_SCK  lshift or
    DD_OUT DD_SS   lshift or DDR_SPI c!
    \ Setup control register
    1           SPR0 lshift
    0           SPR1 lshift or \ fck/16
    CPHA_SMPLED CPHA lshift or
    CPOL_LIDLE  CPOL lshift or
    MSTR_MSTR   MSTR lshift or 
    DORD_MSB    DORD lshift or
    SPE_ENAB    SPE  lshift or
    SPIE_DISAB  SPIE lshift or SPCR c!
;

\ send byte repeatedly with 1 ms delay in between
: rpt-spi-char ( c -- )
    begin dup tx-spi 1 ms again ;

init-spi-ex0  ok<#,ram> 
$de rpt-spi-char
example 0: a common configuration

Here we are transmitting with a 1Mhz clock (fck/16). We have the SCK set to idle on low voltage, with the sample on the lead edge. This means when you see the yellow signal jump up, look down at the green line to see the bit – high for 1 and low for 0. Here we have 11011110, i.e., value 0xDE in Most Significant bit (MSB) order, as expected.

In this slight variation, we sample on the trailing edge of the SCK signal instead:

\ with clock phase sampled on trailing
: init-spi-ex1 ( -- )
    \ set data direction bits
    DD_OUT DD_MOSI lshift
    DD_OUT DD_SCK  lshift or
    DD_OUT DD_SS   lshift or DDR_SPI c!
    \ Setup control register
    1          SPR0 lshift
    0          SPR1 lshift or \ fck/16
    CPHA_SMPTRL CPHA lshift or
    CPOL_LIDLE CPOL lshift or
    MSTR_MSTR  MSTR lshift or 
    DORD_MSB   DORD lshift or
    SPE_ENAB   SPE  lshift or
    SPIE_DISAB SPIE lshift or SPCR c!
;
example 1: sample on trailing edge of SCK

So to determine the bit value, you must look at the value below where the yellow SCK signal falls down to low.

Another variation is to go back to sampling on the leading edge, but have SCK idle on high, so again we must look for the SCK signal to fall down to low.

\ clock polarity high on idle
: init-spi-ex2 ( -- )
    \ set data direction bits
    DD_OUT DD_MOSI lshift
    DD_OUT DD_SCK  lshift or
    DD_OUT DD_SS   lshift or DDR_SPI c!
    \ Setup control register
    1           SPR0 lshift
    0           SPR1 lshift or \ fck/16
    CPHA_SMPLED CPHA lshift or
    CPOL_HIDLE  CPOL lshift or
    MSTR_MSTR   MSTR lshift or 
    DORD_MSB    DORD lshift or
    SPE_ENAB    SPE  lshift or
    SPIE_DISAB  SPIE lshift or SPCR c!
;
example 2: SCK idle on high

In another variation, we can go back to the common configuration, with SCK idle on low, and looking for the leading edge (rise in SCK signal), but instead transmit the bits in Least Significant Bit (LSB) order:

\ LSB data order
: init-spi-ex3 ( -- )
    \ set data direction bits
    DD_OUT DD_MOSI lshift
    DD_OUT DD_SCK  lshift or
    DD_OUT DD_SS   lshift or DDR_SPI c!
    \ Setup control register
    1           SPR0 lshift
    0           SPR1 lshift or \ fck/16
    CPHA_SMPLED CPHA lshift or
    CPOL_LIDLE  CPOL lshift or
    MSTR_MSTR   MSTR lshift or 
    DORD_LSB    DORD lshift or
    SPE_ENAB    SPE  lshift or
    SPIE_DISAB  SPIE lshift or SPCR c!
;
example 3: transmit bits in LSB order

Now you see the bits are 01111011, which reverses to 11011110, i.e., 0xDE.

Our final demonstration variation is the common configuration but at a much slower speed, fck/128, or 125,000 bits/sec in our case.

\ much slower speed
: init-spi-ex4 ( -- )
    \ set data direction bits
    DD_OUT DD_MOSI lshift
    DD_OUT DD_SCK  lshift or
    DD_OUT DD_SS   lshift or DDR_SPI c!
    \ Setup control register
    1           SPR0 lshift
    1           SPR1 lshift or \ fck/128
    CPHA_SMPLED CPHA lshift or
    CPOL_LIDLE  CPOL lshift or
    MSTR_MSTR   MSTR lshift or 
    DORD_MSB    DORD lshift or
    SPE_ENAB    SPE  lshift or
    SPIE_DISAB  SPIE lshift or SPCR c!
;
example 4: slower speed

You see the waveform is the same except one SCK cycle is taking a full 8 microseconds.